Typically, in interconnect fabrication schemes, a dielectric insulating material is inserted between a low-k dielectric material and copper lines capped with cobalt to serve as an etch stop layer in via fabrication, as well as passivation protection for metal lines underneath. The feature sizes of components on integrated circuits have been steadily decreasing for the last several decades, leading to significant challenges in interconnection manufacturing, for example low resistance-capacitance (RC) delay and dimensional scaling. Thus, an alternative material with superior chemical and electrical performance that can accommodate RC delay and dimensional scaling may be useful.
Thus, the inventors have provided improved methods for forming an etch stop layer in an interconnect structure.